1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a floating gate and a control gate of a MOS transistor are formed using two conductive layers, e.g., polysilicon layers.
2. Description of the Related Art
In the field of semiconductor integrated circuits, some elements can electrically update data and store data without supplying a power source voltage to the elements. Such an element is called a non-volatile memory element. As a semiconductor integrated circuit in which the non-volatile memory element is arranged as a memory cell, an EPROM (Erasable and Programmable ROM), an E.sup.2 PROM (Electrically Erasable and Programmable ROM), or the like is known. In the non-volatile memory element arranged in the EPROM or E.sup.2 PROM, a floating gate constituted by a first polysilicon layer for storing data and a control gate constituted by a second polysilicon layer used for controlling writing and reading operations are generally formed.
Steps in manufacturing a memory cell constituted by the above non-volatile memory element will be briefly described below.
(1) A relatively thin gate oxide film is formed in an element region on a semiconductor substrate, and a relatively thick field oxide film is formed in a region other than the element region.
(2) A first polysilicon layer is deposited, and this polysilicon layer is selectively etched. At this time, an etched region is generally called a cell slit.
(3) The first polysilicon layer in a region other than a cell region is selectively etched. This step may be performed simultaneously with the etching step (2) for the cell slit.
(4) After the entire surface of the resultant structure is oxidized, a second polysilicon layer is deposited thereon.
(5) The second polysilicon layer, the oxide film, and the first polysilicon layer in the cell region are selectively etched.
(6) The second polysilicon layer in the region other than the cell region is selectively etched.
(7) Ion implantation is performed to form the source/drain of a MOS transistor for a memory cell.
(8) Contact holes are formed.
(9) A wiring metal layer is formed.
With the above steps, a large number of memory cells each having a two-layered polysilicon structure including a floating gate formed by the first polysilicon layer and a control gate formed by the second polysilicon layer are formed. In addition, the control gate of each of the memory cells also serves as a word line.
In a large number of memory cells manufactured in the above steps, in order to supply an output from a plurality of row decoders to word lines which also serve as control gates, contact holes are formed at the end portion of each of the word lines and at the position of each of the output nodes of the row decoder, and both the contact holes must be connected to each other using a metal wiring line or the like. Since the output nodes of the row decoder are generally formed by a diffusion layer and the control gates are formed by the second polysilicon layer, a signal path must be formed beginning with the diffusion layer first, followed by the contact hole, the metal wiring line, the contact hole, and the second polysilicon layer.
In this case, when a contact hole is to be formed in the second polysilicon layer, the following aspects of the process are important. That is, a contact hole in the diffusion layer and a contact hole in the second polysilicon layer are simultaneously formed. In a photoetching process, a focal depth for a photoresist is important. If the second polysilicon is located on the first polysilicon layer and the oxide film formed thereon, and contact holes are to be formed in the second polysilicon layer, the focal depths for the contact holes formed in the diffusion layer and the second polysilicon layer do not easily have the same condition due to the positional relationship between the diffusion layer and the second polysilicon layer.
FIG. 1 is a plan view of a pattern showing a structure near an output node of a row decoder and an end portion of a word line. FIGS. 2A and 2B are sectional views of different structures along a line 2--2a in FIG. 1. In FIGS. 2A and 2B, reference numeral 60 denotes a semiconductor substrate; 61, a diffusion layer serving as an output node of a row decoder; 62, a first polysilicon layer; 63, a second polysilicon layer; 64, an insulating oxide film; 65 and 66, contact holes formed in the insulating oxide film 64.
As shown in FIG. 2A, when the second polysilicon layer 63 is left on the first polysilicon layer 62, and a beam is focused on the contact hole 66 in the second polysilicon layer 63, the beam is not focused on the contact hole 65 on the diffusion layer 61 because the hole 65 is located at a position much deeper than that of the contact hole 66. For this reason, both the contact holes 65 and 66 are not simultaneously formed, and they must be independently formed in different steps, thereby complicating the steps in manufacturing an integrated circuit.
As a method for solving the above problem, as shown in FIG. 2B, there is a method in which the first polysilicon layer 62 located under the second polysilicon layer 63 is removed in advance. This removal is performed simultaneously with step (3). According to this method, the height of the contact hole 66 on the second polysilicon layer 63 is close to that of the contact hole 65 on the diffusion layer 61, and the contact hole 65 on the diffusion layer 61 and the contact hole 66 on the second polysilicon layer 63 can be simultaneously formed.
FIG. 3 is a plan view of a pattern showing an arrangement of a part of the memory cell array of an EPROM formed in the latter method shown in FIG. 2B, and FIG. 4 is a sectional view showing the memory cell array along a line 4--4a in FIG. 3. In FIGS. 3 and 4, reference numeral 71 denotes a diffusion layer serving as the source or drain of a memory cell transistor; 72, floating gates constituted by a first polysilicon layer; 73, word lines constituted by a second polysilicon layer and serving as a plurality of control gates; 74, cell slits for separating the first polysilicon layer into the floating gates; 75, a removed region from which the first polysilicon layer is removed in advance; and 76, contact holes for connecting bit lines (not shown) to the drains of memory cell transistors.
As shown in FIG. 3, in a conventional method, the removed region 75 of the first polysilicon layer is formed to have large region including the plurality of word lines 73.
As described above, in the conventional method, since the removed region is formed to have the large region including the plurality of word lines, the following inconvenience occurs.
FIGS. 5A to 5E are sectional views sequentially showing the steps of depositing the first and second polysilicon layers, selectively etching these layers, and forming the floating gate and the control gate.
As shown in FIG. 5A, the first polysilicon layer 62 is deposited. As shown in FIG. 5B, a part of the first polysilicon layer 62 is selectively removed to form a removed region 75. At this time, a step difference corresponding to the thickness of the first polysilicon layer 62 is formed at an interface between the first polysilicon layer 62 and the removed region 75. As shown in FIG. 5C, after a gate oxide film 67 is formed, the second polysilicon layer 63 is deposited on the entire surface of the resultant structure. At this time, the step difference corresponding to the thickness of the first polysilicon layer 62 is left. Subsequently, as shown in FIG. 5D, the second polysilicon layer 63, the gate oxide film 67, and the first polysilicon layer 62 are selectively removed by etching in this order. At this time, the second polysilicon layer 63 may not be completely etched such that a part of the second polysilicon layer 63 is often left on a side wall of the gate oxide film 67. Subsequently, as shown in FIG. 5E, the first polysilicon layer 62 on a portion other than a memory cell transistor is selectively removed. At this time, the part of the second polysilicon layer 63 which is left in the etching step is left.
FIG. 6 is a perspective view showing the state at a time when the step of FIG. 5E is finished. As shown in FIG. 5E, if part of the second polysilicon layer 63 remains after the etching step, the word lines 73 are short-circuited with each other by this part of the second polysilicon layer 63.
According to the above conventional method, a first conductive layer is deposited, a part of the first conductive layer is removed, and a second conductive layer is formed thereon. Thereafter, when the second and first conductive layers are selectively removed in sequence, a part of the second conductive layer to be removed is left, the regions of the second conductive layer which must be formed separately from each other in a normal state are disadvantageously short-circuited with each other.